ATA8743-PXQW【PDF 51/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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Sheet目录52

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9152BINDCO02/10

ATA8743

the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator

Control and Status Register ACSR. This will reduce power consumption in Idle mode. If the

ADC is enabled, a conversion starts automatically when this mode is entered.

15.3 ADC Noise Reduction Mode

When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise

Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the

Watchdog to continue operating (if enabled). This sleep mode halts clk

I/O

, clk

CPU

, and clk

FLASH

while allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out

Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change

interrupt can wake up the MCU from ADC Noise Reduction mode.

15.4 Power-down Mode

When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter

Power-down mode. In this mode, the Oscillator is stopped, while the external interrupts, and the

Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a

Brown-out Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the

MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules

only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. See External Interrupts on page 68 for

details

15.5 Standby Mode

When the SM1..0 bits are 11 and an external crystal/resonator clock option is selected, the

SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down

with the exception that the Oscillator is kept running. From Standby mode, the device wakes up

in six clock cycles.

15.6 Power Reduction Register

The Power Reduction Register (PRR), see PRR Power Reduction Register on page 54, pro-

vides a method to stop the clock to individual peripherals to reduce power consumption. The

current state of the peripheral is frozen and the I/O registers can not be read or written.

Resources used by the peripheral when stopping the clock will remain occupied, hence the

peripheral should in most cases be disabled before stopping the clock. Waking up a module,

which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. See Power-down Supply Current on page 212 for examples. In all other

sleep modes, the clock is already stopped.

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